1. Field of the Invention
The present invention relates to the simulation of a complex, large integrated circuit design, and in particular to performing solving and integrating of the nodes of a circuit based on their node topology and physics, which includes both node order and inter-nodal coupling relationships, thereby ensuring a faster, more accurate, more stable, overall simulation of an integrated circuit design.
2. Related Art
Integrated circuit (IC) designs today are becoming increasing complex because of additional desired functionality. Moreover, ever-smaller technology nodes, e.g. down to 45 nm or less, may require design modifications that at 100 nm were unnecessary. Because of these factors, the accurate simulation of these ICs is necessary to ensure proper circuit performance.
Linear network reduction (LNR), which provides simplified models that approximate circuit behavior, can be used during simulation. Indeed, without LNR, a target matrix of a typical IC design is so large that simulating post-layout circuits makes DC analysis (which determines the operating point of a circuit, i.e. defining the initial condition (time=0) of the dynamic components in the circuit) and TR analysis (which uses a transient/time domain, starting at time=0 and through a plurality of clock cycles) extremely slow. Unfortunately, LNR is having significant problems at current technology nodes, e.g. at 45 nm. As described below, these problems can result in significant inaccuracies and even instability.
Note that a circuit can be represented using a graph comprised of nodes and edges, wherein the edges are effectively models of devices and the nodes connect the edges. FIG. 1A illustrates a graph of a simple 3-node circuit having nodes A, B, and C, with edges RAB, RBC, and RAC. FIG. 1B illustrates a graph of an equivalent 4-node circuit that can be created using a delta-wye transformation, wherein the 4-node circuit includes nodes A, B, C, and D and edges RAD, RCD, and RBD.
Notably, the Kirchoff laws can be applied to node/edge graphs. For example, Kirchoff's current law (KCL) states that the algebraic sum of all currents flowing out of and into any circuit node is zero. Thus, in reference to FIG. 1A or 1B, the current flowing into node B is equal to the current flowing out of node B. KCL is therefore described as a nodal equation. On the other hand, Kirchoff's voltage law (KVL) states that the directed sum of the electrical potential differences, i.e. voltages, around any closed circuit must be zero. Thus, the sum of the voltages of the loop formed by nodes A, B, and C in FIG. 1A is equal to zero. KVL is therefore described as a loop equation. Simulation attempts to solve both the KCL and KVL equations at each clock cycle.
SPICE (simulation program with IC emphasis) effectively builds a linear model at an operating point and then constructs one matrix equation, i.e. Ax=b (wherein “A” is an incidence matrix that represents the graph, “x” are the unknowns that represent nodal voltages, branch voltages, and branch currents, and “b” is a known vector column contributed by ideal sources, which is shown in FIG. 2. The matrix “A” can include KCL (linear) equations, KVL (linear) equations, and I-V (current-voltage) (non-linear) equations. Note that a modified nodal analysis (MNA) can be used instead of the matrix equation shown in FIG. 2. This MNA approach is described, for example, in “The Modified Nodal Analysis to Network Analysis”, Chung-Wen Ho et al., IEEE Transactions On Circuits And Systems, VOL. CAS-22, NO. 6, June 1975. Notably, the MNA approach also includes a matrix equation that exhibits the same disadvantages as those described in reference to FIG. 2. Those skilled in the art of circuit simulation understand various matrix equations, which are therefore not explained in further detail herein. Because of its simplicity, the matrix equation shown in FIG. 2 is used for explanation purposes.
In general, linear equations have derivatives higher than the first order equal to zero, whereas non-linear equations have non-zero derivatives higher than the first order, as expressed by the Taylor series, shown below for reference and which is known by those skilled in the art of simulation.
      ∑          n      =      0        ∞    ⁢                              f                      (            n            )                          ⁡                  (          a          )                            n        !              ⁢                  (                  x          -          a                )            n      
where n! denotes the factorial of n and f(n) denotes the nth derivative of f evaluated at the point a (the zeroth derivative of f being defined to be f) (wherein (x−a)0 and 0! are defined to be 1). To solve Ax=b, one direct method is x=A−1b. Another more typical method for circuit simulation is an iterative approach that requires convergence.
Unfortunately, mixing linear and non-linear equations in the matrix causes unnecessary matrix calculations for the linear equations. That is, solving for non-linear components requires more iterations than solving for linear components. If non-linear components are represented in the matrix, then linear components are subject to the same number of iterations performed for the highest order non-linear component (i.e. the non-linear component having the highest number of corresponding derivatives to accurately describe its behavior). Because of the single matrix used as well as linear/non-linear mixing in that matrix and its requisite iterations, SPICE is typically used to simulate ICs having relatively few circuits (e.g. ICs having under 100,000 gates).
Fast SPICE is a technique for speeding up simulation for large, highly complex ICs (e.g. ICs having over 1 million gates). To achieve this goal, Fast SPICE partitions a design into multiple parts, thereby allowing multiple matrices to be used. Exemplary Fast SPICE implementations are represented in FIGS. 3A and 3B. For example, FIG. 3A illustrates a conventional flattened structure including regions 1, 2, and 3. In this case, the original matrix is split into a number of weekly coupled regions based on circuit topology and the underlying device physics, which are solved in a quasi-independent manner. Coupling between the circuit regions is reintroduced by a variety of techniques external to the matrix solution. Exemplary simulation products offered by Synopsys, Inc. using this flattened structure include NanoSim® and XA™. FIG. 3B illustrates an exemplary, simplified hierarchical structure in which sub-circuit 1 includes sub-circuits 2 and 3, and sub-circuit 3 includes sub-circuit 4. In this case, the matrix solver attempts to make use of repeated patterns within the matrix structure that reflect the underlying circuit's hierarchical design. Exemplary simulation products offered by Synopsys, Inc. using this hierarchical structure include HSIM®. Unfortunately, for either implementation, mixing linear/non-linear devices and nodes in a region/sub-circuit can cause significant inaccuracies (just as with a single matrix). Further, coupling can occur between regions/sub-circuits, thereby requiring further modeling (and simulation time) or risk increasing simulation inaccuracies.
Therefore, a need arises for an improved technique that provides accurate simulation for large, complex ICs including both linear and non-linear components.